Operator: ReLU6-Affine-Gate (Fused CUDA Kernel)

Goal
- Fuse affine transform, ReLU6 activation, sigmoid gate, and multiply to reduce memory traffic and kernel launches, targeting ≥1.30x speedup.

Inputs/Outputs
- Input `x`: [B, D], float32
- Parameters `scale`, `bias`: [D], float32
- Scalars `alpha`, `beta`: float32
- Output `y`: [B, D], float32

Definition
- z = x * scale + bias
- m = clamp(z, 0, 6)
- g = sigmoid(alpha * m + beta)
- y = x * g

CUDA Design
- 2D grid with float4 vectorization, block=256, ILP=2 per thread
- FMA for affine, fast math for sigmoid, branchless clamp
- Pass `alpha`, `beta` as plain scalars to avoid host-device sync

Validation
- Accuracy: torch.allclose(rtol=1e-3) vs PyTorch reference
- Performance: speedup ≥ 1.30x at B=16, D=16384

How to Run
- Execute `run_code.py` to verify precision and timing
